1. Field
This disclosure relates generally to multiple data rate memories and more particularly, with timing information for aiding in performing a read of data provided by the memory.
2. Related Art
Multiple data rate memories have become very popular, especially for DRAMs but also other types of memories such as non-volatile memories. Most commonly they are double data rate (DDR) memories in which data is provided on both halves of a clock cycle. In a read of the DDR memory by a controller, the data is provided by the DDR memory in a burst of data that is accompanied by a data strobe signal, sometimes referenced as a DQS signal, that provides assistance to the controller in reading the data. This data, arriving at twice the clock frequency, pushes the limits of being able to be read. The DQS signal is delayed very carefully by DQS circuitry in the controller so that the data can be properly read. This DQS circuitry is typically very critical in achieving effective reading but the circuitry can be sensitive to temperature and voltage as well as process variations. Thus, an effective design of the DQS circuitry can be time consuming and require much more space than would normally be expected of a delay circuit. Due to the sensitivity of the DQS circuitry, a process improvement can actually create reliability problems for this delay circuit.
Accordingly there is a need to provide further improvement in providing timing for data being read from a multiple data rate memory.